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? 2005 fairchild semiconductor corporation ds500447 www.fairchildsemi.com august 2001 revised october 2006 fstud32450 configurable 4-bit to 40-bit bus switch with 2v undershoot protection and selectable level shifting fstud32450 configurable 4-bit to 40-bit bus switch with 2v undershoot protection and selectable level shifting general description the fairchild universal bus switch fstud32450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed cmos ttl-compatible bus switching. the low on resis- tance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. the fstud32450 is designed to allow ?customer? configu- ration control of the enable connections. the device can be organized as either a ten 4-bit, eight 5-bit, four 10-bit, two 20-bit or one 40-bit enabled bus switch. also achievable are 8-bit and 16-bit enabled configurations (see functional description). the device's bit configuration is controlled through select pin logic. (see truth table). when oe x is low, port a x is connected to port b x . when oe x is high, the switch is open. the a and b ports are protected against undershoot to support an extended range to 2.0v below ground. fairchild's integrated undershoot hardened circuit (uh c? ) senses undershoot at the i/o, and responds by preventing voltage differentials from developing and turning the switch on. another innovative device feature is the addition of a level shifting select pin, ?s 2 and s 5 ?. when s 2 and s 5 are low, the device behaves as a standard n-mos switch. when s 2 and s 5 are high, a diode to v cc is integrated into the cir- cuit allowing for level shifting between 5v inputs and 3.3v outputs. features undershoot protected to 2v (a and b ports) voltage level shifting 4 : switch connection between two ports minimal propagation delay through the switch low l cc zero bounce in flow-through mode control inputs compatible with ttl level see applications notes an-5008 and an-5021 for uhc details packaged in plastic fine-pitch ball grid array (fbga) applications note select pins s 0 , s 1 , s 2 , s 3 , s 4 and s 5 are intended to be used as static user configurable control pins. the ac per- formance of these pins has not been characterized or tested. switching of these select pins during system opera- tion may temporarily disrupt output logic states and/or enable pin controls. 40-bit configuration can be achieved by connecting the oe 1 and the oe 6 pins to together. ordering code: note 1: ordering code ? g ? indicates trays. note 2: devices also available in tape and reel. specify by appending the suffix letter ? x ? to the ordering code. uhc ? is a registered trademark of fairchild semiconductor corporation. order number package number package description fstud32450g (note 1)(note 2) bga114a 114-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide
www.fairchildsemi.com 2 fstud32450 connection diagram pin assignment for fbga (top thru view) pin descriptions fbga pin assignments pin name description oe 1 , oe 2 , oe 3 , oe 4 , bus switch oe 5 , oe 6 , oe 7 , oe 8 enables oe 9 , oe 10 1a, 2a, 3a, 4a bus a 1b, 2b, 3b, 4b bus b s 0 , s 1 , s 3 , s 4 bit configuration enables s 2 , s 5 level shifting diode enables 12 3 456 a 1a 4 1a 2 oe 1 oe 2 1b 2 1b 4 b 1a 6 1a 5 1a 1 1b 1 1b 5 1b 6 c 1a 8 1a 7 1a 3 1b 3 1b 7 1b 8 d 1a 10 1a 9 gnd oe 5 1b 9 1b 10 e 2a 2 2a 1 s 0 v cc 2b 1 2b 2 f 2a 4 2a 3 s 1 s 2 2b 3 2b 4 g 2a 6 2a 5 v cc gnd 2b 5 2b 6 h 2a 8 2a 7 gnd gnd 2b 7 2b 8 j 2a 10 2a 9 gnd gnd 2b 9 2b 10 k oe 4 oe 8 gnd gnd oe 9 oe 3 l 3a 10 3a 9 gnd gnd 3b 9 3b 10 m 3a 8 3a 7 gnd gnd 3b 7 3b 8 n 3a 6 3a 5 gnd v cc 3b 5 3b 6 p 3a 4 3a 3 s 5 s 4 3b 3 3b 4 r 3a 2 3a 1 v cc s 3 3b 1 3b 2 t 4a 10 4a 9 oe 10 gnd 4b 9 4b 10 u 4a 8 4a 7 4a 3 4b 3 4b 7 4b 8 v 4a 6 4a 5 4a 1 4b 1 4b 5 4b 6 w 4a 4 4a 2 oe 7 oe 6 4b 2 4b 4
3 www.fairchildsemi.com fstud32450 logic diagrams 20-bit configuration 10-bit configuration
www.fairchildsemi.com 4 fstud32450 5-bit configuration 4-bit configuration
5 www.fairchildsemi.com fstud32450 functional description the device can also be configured as an 8 and 16-bit device by grounding the unused pins in configurations 2 and 1 respectively. the 8-bit configuration may also be achieved by tying two of the 4-bit enables from configuration together and tying the remaining enable pin (oe ) high. truth tables (x v cc or gnd) (see functional description) select pin s 2 , s 5 mode l std. nmos switch h level shifting diode enabled 20-bit configuration (s 0 s 1 l) inputs inputs/outputs oe 1 oe 2 oe 3 oe 4 oe 5 lxxxx 1a 1-10 1b 1-10 , 2a 1-10 2b 1-10 hxxxx z s 3 s 4 l inputs inputs/outputs oe 6 oe 7 oe 8 oe 9 oe 10 lxxxx 3a 1-10 3b 1-10 , 4a 1-10 4b 1-10 hxxxx z 10-bit configuration (s 0 l, s 1 h) inputs inputs/outputs oe 1 oe 2 oe 3 oe 4 oe 5 1a 1-10 1b 1-10 2a 1-10 2b 1-10 lxxlx 1a x 1b x 2a x 2b x lxxhx 1a x 1b x z hxxlx z 2a x 2b x hxxhx z z s 3 l, s 4 h inputs inputs/outputs oe 6 oe 7 oe 8 oe 9 oe 10 4a 1-10 4b 1-10 3a 1-10 3b 1-10 lxxlx 4a x 4b x 3a x 3b x lxxhx 4a x 4b x z hxxlx z 3a x 3b x hxxhx z z
www.fairchildsemi.com 6 fstud32450 truth tables (continued) 5-bit configuration (s 0 h, s 1 l) inputs inputs/outputs oe 1 oe 2 oe 3 oe 4 oe 5 1a 1-5 , 1b 1-5 1a 6-10 , 1b 6-10 2a 1-5 , 2b 1-5 2a 6-10 , 2b 6-10 llllx1a x 1b x 1a y 1b y 2a x 2b x 2a y 2b y lllhx1a x 1b x 1a y 1b y 2a x 2b x z llhlx1a x 1b x 1a y 1b y z2a y 2b y llhhx1a x 1b x 1a y 1b y zz lhllx1a x 1b x z2a x 2b x 2a y 2b y lhlhx1a x 1b x z2a x 2b x z lhhlx1a x 1b x zz2a y 2b y lhhhx1a x 1b x zzz hlllx z 1a y 1b y 2a x 2b x 2a y 2b y hllhx z 1a y 1b y 2a x 2b x z hlhlx z 1a y 1b y z2a y 2b y hlhhx z 1a y 1b y zz hhl l x z z 2a x 2b x 2a y 2b y hhlhx z z 2a x 2b x z hhhl x z z z 2a y 2b y hhhhx z z z z s 3 h, s 4 l inputs inputs/outputs oe 6 oe 7 oe 8 oe 9 oe 10 4a 1-5 , 4b 1-5 4a 6-10 , 4b 6-10 3a 1-5 , 3b 1-5 3a 6-10 , 3b 6-10 llllx4a x 4b x 4a y 4b y 3a x 3b x 3a y 3b y lllhx4a x 4b x 4a y 4b y 3a x 3b x z llhlx4a x 4b x 4a y 4b y z3a y 3b y llhhx4a x 4b x 4a y 4b y zz lhllx4a x 4b x z3a x 3b x 3a y 3b y lhlhx4a x 4b x z3a x 3b x z lhhlx4a x 4b x zz3a y 3b y lhhhx4a x 4b x zzz hlllx z 4a y 4b y 3a x 3b x 3a y 3b y hllhx z 4a y 4b y 3a x 3b x z hlhlx z 4a y 4b y z3a y 3b y hlhhx z 4a y 4b y zz hhl l x z z 3a x 3b x 3a y 3b y hhlhx z z 3a x 3b x z hhhl x z z z 3a y 3b y hhhhx z z z z
7 www.fairchildsemi.com fstud32450 truth tables (continued) 4-bit configuration (s 0 s 1 h) inputs inputs/outputs oe 1 oe 2 oe 3 oe 4 oe 5 1a 1-4 , 1b 1-4 1a 5-8 , 1b 5-8 2a 3-6 , 2b 3-6 2a 7-10 , 2b 7-10 1a 9-10 , 2b 9-10 2a 1-2 , 2b 1-2 lllll1a x 1b x 1a y 1b y 2a x 2b x 2a y 2b y 1a z 1b z 2a z 2b z llllh1a x 1b x 1a y 1b y 2a x 2b x 2a y 2b y z lllhl1a x 1b x 1a y 1b y 2a x 2b x z 1a z 1b z 2a z 2b z lllhh1a x 1b x 1a y 1b y 2a x 2b x zz llhll1a x 1b x 1a y 1b y z2a y 2b y 1a z 1b z 2a z 2b z llhlh1a x 1b x 1a y 1b y z2a y 2b y z llhhl1a x 1b x 1a y 1b y zz 1a z 1b z 2a z 2b z llhhh1a x 1b x 1a y 1b y zzz lhlll1a x 1b x z2a x 2b x 2a y 2b y 1a z 1b z 2a z 2b z lhllh1a x 1b x z2a x 2b x 2a y 2b y z lhlhl1a x 1b x z2a x 2b x z 1a z 1b z 2a z 2b z lhlhh1a x 1b x z2a x 2b x zz lhhll1a x 1b x zz2a y 2b y 1a z 1b z 2a z 2b z lhhlh1a x 1b x zz2a y 2b y z lhhhl1a x 1b x zzz 1a z 1b z 2a z 2b z lhhhh1a x 1b x zzzz hllll z 1a y 1b y 2a x 2b x 2a y 2b y 1a z 1b z 2a z 2b z hlllh z 1a y 1b y 2a x 2b x 2a y 2b y z hllhl z 1a y 1b y 2a x 2b x z 1a z 1b z 2a z 2b z hllhh z 1a y 1b y 2a x 2b x zz hlhll z 1a y 1b y z2a y 2b y 1a z 1b z 2a z 2b z hlhlh z 1a y 1b y z2a y 2b y z hlhhl z 1a y 1b y zz 1a z 1b z 2a z 2b z hlhhh z 1a y 1b y zzz hhl l l z z 2a x 2b x 2a y 2b y 1a z 1b z 2a z 2b z hhl lh z z 2a x 2b x 2a y 2b y z hhlhl z z 2a x 2b x z 1a z 1b z 2a z 2b z hhlhh z z 2a x 2b x zz hhhl l z z z 2a y 2b y 1a z 1b z 2a z 2b z hhhlh z z z 2a y 2b y z hhhhl z z z z 1a z 1b z 2a z 2b z hhhhh z z z z z
www.fairchildsemi.com 8 fstud32450 truth tables (continued) 4-bit configuration (continued) s 3 s 4 h inputs inputs/outputs oe 6 oe 7 oe 8 oe 9 oe 10 4a 1-4 , 4b 1-4 4a 5-8 , 4b 5-8 3a 3-6 , 3b 3-6 3a 7-10 , 3b 7-10 3a 1-2 , 3b 1-2 4a 9-10 , 3b 9-10 lllll4a x 4b x 4a y 4b y 3a x 3b x 3a y 3b y 3a z 3b z 4a z 4b z llllh4a x 4b x 4a y 4b y 3a x 3b x 3a y 3b y z lllhl4a x 4b x 4a y 4b y 3a x 3b x z 3a z 3b z 4a z 4b z lllhh4a x 4b x 4a y 4b y 3a x 3b x zz llhll4a x 4b x 4a y 4b y z3a y 3b y 3a z 3b z 4a z 4b z llhlh4a x 4b x 4a y 4b y z3a y 3b y z llhhl4a x 4b x 4a y 4b y zz 3a z 3b z 4a z 4b z llhhh4a x 4b x 4a y 4b y zzz lhlll4a x 4b x z3a x 3b x 3a y 3b y 3a z 3b z 4a z 4b z lhllh4a x 4b x z3a x 3b x 3a y 3b y z lhlhl4a x 4b x z3a x 3b x z 3a z 3b z 4a z 4b z lhlhh4a x 4b x z3a x 3b x zz lhhll4a x 4b x zz3a y 3b y 3a z 3b z 4a z 4b z lhhlh4a x 4b x zz3a y 3b y z lhhhl4a x 4b x zzz 3a z 3b z 4a z 4b z lhhhh4a x 4b x zzzz hllll z 4a y 4b y 3a x 3b x 3a y 3b y 3a z 3b z 4a z 4b z hlllh z 4a y 4b y 3a x 3b x 3a y 3b y z hllhl z 4a y 4b y 3a x 3b x z 3a z 3b z 4a z 4b z hllhh z 4a y 4b y 3a x 3b x zz hlhll z 4a y 4b y z3a y 3b y 3a z 3b z 4a z 4b z hlhlh z 4a y 4b y z3a y 3b y z hlhhl z 4a y 4b y zz 3a z 3b z 4a z 4b z hlhhh z 4a y 4b y zzz hhl l l z z 3a x 3b x 3a y 3b y 3a z 3b z 4a z 4b z hhl lh z z 3a x 3b x 3a y 3b y z hhlhl z z 3a x 3b x z 3a z 3b z 4a z 4b z hhlhh z z 3a x 3b x zz hhhl l z z z 3a y 3b y 3a z 3b z 4a z 4b z hhhlh z z z 3a y 3b y z hhhhlzzzz 3a z 3b z 4a z 4b z hhhhh z z z z z
9 www.fairchildsemi.com fstud32450 absolute maximum ratings (note 3) recommended operating conditions (note 6) note 3: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 4: v s is the voltage observed/applied at either the a or b ports across the switch. note 5: the input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. note 6: unused control inputs must be held high or low. they may not float. dc electrical characteristics note 7: typical values are at v cc 5.0v and t a 25 q c note 8: measured by the voltage drop between a and b pins at the indicated current through the switch. on resistance is determined by t he lower of the voltages on the two (a or b) pins. supply voltage (v cc ) 0.5v to 7.0v dc switch voltage (v s ) (note 4) 2.0v to 7.0v dc input control pin voltage (v in ) (note 5) 0.5v to 7.0v dc input diode current (l ik ) v in 0v 50 ma dc output (i out ) current 128 ma dc v cc /gnd current (i cc /i gnd ) / 100 ma storage temperature range (t stg ) 65 q c to 150 q c power supply operating (v cc) 4.0v to 5.5v input voltage (v in ) 0v to 5.5v output voltage (v out ) 0v to 5.5v free air operating temperature (t a )-40 q c to 85 q c symbol parameter v cc t a 40 q c to 85 q c units conditions (v) min typ (note 7) max v ik clamp diode voltage 4.5 1.2 v i in 18 ma v ih high level input voltage 4.0-5.5 2.0 v if s 2 high 4.5v d v cc d 5.5v v il low level input voltage 4.0-5.5 0.8 v if s 2 high 4.5v d v cc d 5.5v v oh high level output voltage 4.5-5.5 see figure 4 v s 2 s 5 v cc i i input leakage current 5.5 r 1.0 p a0 d v in d 5.5v 010 p av in 5.5v i oz off-state leakage current 5.5 r 1.0 p a0 d a, b d v cc r on switch on resistance 4.5 4 7 : v in 0v, i in 64 ma, s 2 s 5 0v or v cc (note 8) 4.5 4 7 : v in 0v, i in 30 ma, s 2 s 5 0v or v cc 4.5 8 12 : v in 2.4v, i in 15 ma, s 2 s 5 0v 4.0 11 20 : v in 2.4v, i in 15 ma, s 2 s 5 0v 4.5 35 50 : v in 2.4v, i in 15 ma, s 2 s 5 v cc i cc quiescent supply current 5.5 3 p as 2 s 5 gnd, v in v cc or gnd, i out 0 10 p as 2 s 5 v cc , oe x v cc , v in v cc or gnd, i out 0 1.5 ma s 2 s 5 v cc , oe x gnd, v in v cc or gnd, i out 0 i cct increase in i cc per 5.5 2.5 ma one control input at 3.4v control input other inputs at v cc or gnd, s 2 0v 4.0 ma one control input at 3.4v other inputs at v cc or gnd, s 2 v cc v iku voltage undershoot 5.5 2.0 v 0.0 ma t i in t 50 ma oe x 5.5v
www.fairchildsemi.com 10 fstud32450 ac electrical characteristics note 9: this parameter is guaranteed by design but is not tested. the bus switch contributes no propagation delay other than the rc del ay of the typical on resistance of the switch and the 50pf load capacitance, when driven by an ideal voltage source (zero output impedance). ac electrical characteristics: translating diode note 10: this parameter is guaranteed by design but is not tested. this bus switch contributes no propagation delay other than the rc de lay of the typical on resistance of the switch and the 50pf load capacitance, when driven by an ideal voltage source (zero output impedance). capacitance (note 11) note 11: t a 25 q c, f 1 mhz, capacitance is characterized but not tested. symbol parameter t a 40 q c to 85 q c, units c l 50pf, ru rd 500 : conditions figure v cc 4.5 ? 5.5v v cc 4.0v (s 2 s 5 0v) number min max min max t phl , t plh propagation delay bus-to-bus (note 9) 0.25 0.25 ns v i open figures 2, 3 t pzh , t pzl output enable time 1.5 6.5 7.0 ns v i 7v for t pzl figures 2, 3 v i open for t pzh t phz , t plz output disable time 1.5 6.7 7.2 ns v i 7v for t plz figures 2, 3 v i open for t phz t pzh , t pzl s el (s 0, 1 ) to output enable time 1.5 7.0 7.5 ns v i 7v for t pzl figures 2, 3 v i open for t pzh t phz , t plz s el (s 0, 1 ) to output disable time 1.5 7.5 7.7 ns v i 7v for t plz figures 2, 3 v i open for t phz symbol parameter t a 40 q c to 85 q c, units c l 50pf, ru rd 500 : conditions figure v cc 4.5 ? 5.5v (s 2 s 5 v cc ) number min max t phl , t plh propagation delay bus-to-bus (note 10) 0.25 ns v i open figures 2, 3 t pzh , t pzl output enable time 1.5 10.0 ns v i 7v for t pzl figures 2, 3 v i open for t pzh t phz , t plz output disable time 1.5 9.0 ns v i 7v for t plz figures 2, 3 v i open for t phz t pzh , t pzl s el (s 0, 1 ) to output enable time 1.5 11.0 ns v i 7v for t pzl figures 2, 3 v i open for t pzh t phz , t plz s el (s 0, 1 ) to output disable time 1.5 10.0 ns v i 7v for t plz figures 2, 3 v i open for t phz symbol parameter typ max units conditions c in control pin input capacitance 4 pf v cc 5.0v, v in 0v c i/o input/output capacitance ? off state ? 8pfv cc , oe 5.0v, v in 0v
11 www.fairchildsemi.com fstud32450 undershoot characteristic (note 12) note 12: this test is intended to characterize the device ? s protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event. figure 1. device test conditions transient input voltage (v in ) waveform ac loading and waveforms note: input driven by 50 : source terminated in 50 : note: c l includes load and stray capacitance note: input frequency 1.0 mhz, t w 500 ns figure 2. ac test circuit figure 3. ac waveforms symbol parameter min typ max units conditions v outu output voltage during undershoot 2.5 v oh 0.3 v s 2 s 5 0v, figure 1 tbd tbd v s 2 s 5 v cc parameter value units v in see waveform v r 1 r 2 100k : v tri 11.0 v v cc 5.5 v
www.fairchildsemi.com 12 fstud32450 figure 4.
13 www.fairchildsemi.com fstud32450 configurable 4-bit to 40-bit bus switch with 2v undershoot protection and selectable level shifting physical dimensions inches (millimeters) unless otherwise noted 114-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga114a technology description the fairchild switch family derives from and embodies fairchild ? s proven switch technology used for several years in its 74lvx3l384 (fst3384) bus switch product. fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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